Test MP+dmb.sy+addr-ctrl-rfi-[fr-rf]-ctrl

AArch64 MP+dmb.sy+addr-ctrl-rfi-[fr-rf]-ctrl
"DMB.SYdWW Rfe DpAddrdR DpCtrldW Rfi FrLeave RfBack DpCtrldR Fre"
Cycle=Rfi FrLeave RfBack DpCtrldR Fre DMB.SYdWW Rfe DpAddrdR DpCtrldW
Relax=
Safe=Rfi Rfe Fre DMB.SYdWW DpAddrdR DpCtrldW DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpAddrdR DpCtrldW Rfi FrLeave RfBack DpCtrldR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X6=a; 1:X10=x;
2:X1=a;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | LDR W0,[X1]         | MOV W0,#2   ;
 STR W0,[X1] | EOR W2,W0,W0        | STR W0,[X1] ;
 DMB SY      | LDR W3,[X4,W2,SXTW] |             ;
 MOV W2,#1   | CBNZ W3,LC00        |             ;
 STR W2,[X3] | LC00:               |             ;
             | MOV W5,#1           |             ;
             | STR W5,[X6]         |             ;
             | LDR W7,[X6]         |             ;
             | LDR W8,[X6]         |             ;
             | CBNZ W8,LC01        |             ;
             | LC01:               |             ;
             | LDR W9,[X10]        |             ;
Observed
    y=1; x=1; a=2; 1:X9=0; 1:X8=2; 1:X7=2; 1:X0=1;